1. Field of the Invention
The present invention relates in general to a liquid crystal display device. More particularly, it relates to a liquid crystal display device with a capacitance-compensated structure.
2. Description of the Related Art
Due to the characteristics of thin profile, low power consumption, and lower driving voltage, liquid crystal displays (LCDs) have been widely used in flat panel displays. Owing to dielectric anisotropy and conductive anisotropy of liquid crystal molecules, molecular orientation of liquid crystals can be shifted under an external electric field, such that various optical effects are produced. Generally, the display area of a LCD comprises a plurality of pixel areas and each pixel area further comprises a pair of gate lines (scan line) and a pair of data lines to define a rectangular region. A thin film transistor (TFT), serving as a switching device, and a pixel electrode are disposed in the rectangular region.
FIG. 1 is a plane view of the conventional liquid crystal display device. In FIG. 1, the dotted line region indicates a thin film transistor T, which comprises a gate G, a source S, and a drain D. the gate G extends from a gate line 12 formed by process M1 (first metal layer). A data line 22 and the metal portions of the source S and the drain D are formed by process M2 (second metal layer). The symbol 18 indicates a channel protection layer and the symbol 24 indicates a pixel electrode. A gate-drain parasitic capacitor Cgd is formed between the gate G and the drain D. A gate-source parasitic capacitor Cgs is formed between the gate G and the source S. The capacitances of the gate-drain parasitic capacitor Cgd and the gate-source parasitic capacitor Cgs are changed when alignment shift occurs after processes M1 and M2. For example, when the second metal layer shifts towards the left side (the source S and the drain D shift toward the left side), the capacitance of the gate-drain parasitic capacitor Cgd is increased and that of the gate-source parasitic capacitor Cgs is reduced. Conversely, when the second metal layer shifts towards the right side (source S and drain D shift toward the right side), the capacitance of the gate-drain parasitic capacitor Cgd is reduced and that of the gate-source parasitic capacitor Cgs is increased.
FIG. 2 is an equivalent circuit diagram of the conventional liquid crystal display device. As shown in FIG. 2, the changed capacitance of the gate-source parasitic capacitor Cgs does not directly affect the liquid crystal cell 36. The changed capacitance of the gate-drain parasitic capacitor Cgd, however, changes the voltage applied to the liquid crystal cell 36. This is because the gate-drain parasitic capacitor Cgd is serially connected to the corresponding parallel circuit 36a of the liquid crystal cell 36 and the storage capacitor Cst (not shown in FIG. 1). When the thin film transistor T is turned off, the serially connected gate-drain parasitic capacitor Cgd reduces the voltage on the liquid crystal cell 36, inducing mura effect during operation of the liquid crystal display.